Field of the Invention
The present invention relates generally to the field of video processing and, more specifically, to a data path and an instruction set for packed pixel operations for video processing.
Description of the Related Art
A graphics processing unit (GPU) is a specialized processor that is configured to efficiently process complex graphics and other numerical computations. Each GPU has several on-chip hardware components, such as memory caches and logic operations units, configured to efficiently perform the graphics and numerical computations. In a typical GPU, integer operations are performed within 32-bit integer operations data paths. These 32-bit integer data paths often include arithmetic units and other logic units configured to perform integer operations. Further, these 32-bit integer data paths are configured to operate in a single-instruction, multiple-data (SIMD) fashion.
When processing video and pixel data within a GPU, the 32-bit integer data paths can be used. However, most video and pixel data processing operations, such as sum of absolute differences, pixel differencing and clamping pixel values, operate on 16-bit or 8-bit operands. Therefore, to process video and pixel data on the 32-bit integer data path, the 16-bit or 8-bit operands need to be extracted to 32-bit registers. Such extraction operations not only waste processing cycles, but also waste register space thus negatively affecting the overall performance of the GPU. In addition, video and pixel data is often not aligned to benefit from SIMD-style processing, thus, not making the most efficient use of the 32-bit integer data paths available within the GPU.
As the foregoing illustrates, what is needed in the art is a video processing data path that is configured to efficiently process video and pixel data within a GPU.